Sunday, May 28, 2017

A 6502 CPU for the RC2014 Part 1

The RC2014 design is based on the Z80 8-bit microprocessor.

As far as 1970s-era microprocessor design is concerned, the Z80 and 6502 are on polar opposites. The Z80 is based on the Intel 8080 whereas the 6502 is based on the Motorola 6800.

The design philosophies are very different:
- The 6800 and 6502 use a strict synchronous bus. Each memory or I/O access cycle completes within a single clock system. The clock signal is also used to gate the read and write control lines to memory and peripherals.
- The 8080 and Z80 use a loosely asynchronous bus where the memory or I/O access cycles take a variable number of clock cycles to complete. The clock signal is not used to gate read/write access. Unless you want to generate wait states for slow peripherals or use Zilog Z80-specific parts (PIO, CTC etc) in your design, you can safely ignore the clock signal.

So how would you go about building a 6502 CPU board for the RC2014 system?

The RC2014 bus was designed in a very similar way to the S100 bus: where the latter is based on the 8080 signals, the RC2014 bus signals are just Z80 signals.

Let's look at each of the Z80 signals and see how we can generate their equivalent from the 6502. We will only consider the signals that are actively used to access memory and I/O. Signals like RFSH, BUSRQ, WAIT, BUSAK, HALT, NMI are not routed on the base RC2014 system and we'll ignore them for now.

M1

Let's start with a signal that we don't care about. The Z80 M1 signal is used with the IORQ signal to indicate an interrupt acknowledge cycle. This is only really used for Z80 peripheral devices like the Z80 PIO, CTC or SIO. Since the 6502 by default grabs interrupt vectors from high memory, we can tie M1 to Vcc.

RD & WR

These are the read and write signals for memory and I/O. The 6502 has a combined signal R/W which is high for read and low for write. In 6502 designs, the R/W is usually gated with the Phi2 clock to generate separate read and write lines. This is what we will do here.

IORQ

The Z80 (and 8080) have a dedicated I/O address space that is separate from memory. The 6502 does not have anything similar. Instead, its I/O address space is part of its 64KB space: what we referred to in more modern terms as memory-mapped I/O.

6502 designs generally carve out part of the 64KB address space for peripherals. We will do this in our design: we will map out a 256-byte address space for use with the RC2014 bus. The IORQ signal will be decoded and active low when this address space is accessed by the 6502 CPU.

MREQ

As far as the 6502 is concerned, anything that is not used by I/O can be considered memory, so we generate the MREQ signal by inverting the IORQ signal.

Schematic

The design that we come up with is as follows:

IC2 is a 74HCT688 that is used to decode the 256-byte I/O space. Its output is IORQ and is also inverted by IC1E to generate MREQ

The RD and WR signals are generated by a pair of NAND gates (IC4A & B) and an inverter (IC1C).

When you look at the design carefully, you will realize that IC1F inverts the A15 signal from the 6502. What is that for?

In addition to the difference in bus design philosophies, the Z80/8080 and 6502/6800 families differ in one critical area. The Z80/8080 place their reset and interrupt vectors in low memory. The first instruction after a reset is fetched from address 0000h. On the other hand, the 6502/6800 place their reset and interrupt vectors at the top of memory. The address of the first instruction after a reset (on the 6502) is fetched from FFFCh.

The result of this is that in Z80 systems like the RC2014, ROM memory is at the bottom of the memory space and RAM memory is placed at the top. The base RC2014 RAM board has its RAM mapped from 8000h-FFFFh, for example. On the other hand, 6502 designs will place RAM at the bottom of memory (starting at 0000h) and ROM at the top (finishing at FFFFh).

Therefore in order to cleanly map a 6502 CPU into a typical RC2014 memory configuration, we invert the A15 signal of the 6502. This essentially flips the memory map around so that the base RC2014 RAM board will be seen as mapping its RAM at 0000h-7FFFh. The RC2014 ROM boards are a little more complicated but can be made to work.

The A15 jumper strip allows you to select whether to use the inverted A15 signal.

I/O Mapping

What about I/O mapping? In our design, the 74HCT688 will decode the I/O space to be between C000h and C0FFh. This means that if you know the Z80 port address of a given peripheral, you can figure out the 6502 address of the peripheral by adding C000h to the port address.

Board design

The next picture shows the final board design:
And the populated board:

Note that the JP1 jumper is needed only if you are using the Western Design Center 65C02. It is used to ground the VPB line.

Eagle design files can be found at GitHub.

Boards can be ordered from OSH Park by clicking on the following icon
Order from OSH Park


The next installment (Part 2) will cover how to use this board with an RC2014 system and will briefly touch on the software.










4 comments:

  1. Replies
    1. I just posted a note about a 6809 CPU board that I'd developed for the RC2014. I'll looking into building up a monitor/debugger for that.

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  2. Have a look at the C128 from Commodore, there a Z80 and a 6510 live in harmony ;o) Why not using CPLD or FPGA devices for all that adress-decoding and area-switching stuff? So even a self-reconfigurable solution would be possible if you place the processor-specific ini-routines in a small xyROM directly on the CPU-Board and write some Software to allow all the other functions to adopt according to the virtual memory/IO-Map needed!

    beneath: Memory-Mapped-IO as term was already in use in the early eighties!

    So only 6502 is real von Neumann machine, Z80 and i80xx is a little harvard-infected. (6502 is also the first and only real RISC-Maschine, the engineers of ARM were very deeply involved in 6502 programming when they started to build the first ARM-core!) So forget about Z80 and go for 65C816 for real performance!

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  3. I am looking forward to your next installment!

    ReplyDelete